Moore's law: transistor growth and its costs
Moore's law describes an observation about the number of transistors in an integrated circuit: it doubles about every two years, with minimal increase in cost. The name gives this empirical relationship the sound of a scientific law, but its foundation is observed industrial progress. It is an experience curve effect, connecting efficiency gains with learning in production. The observation is named after Gordon Moore, co-founder of Fairchild Semiconductor and Intel. His evidence captured a historical trend; it did not establish that the same pace must continue indefinitely. The distinction matters when a manufacturing pattern becomes a forecast for an entire industry.
The original forecast began at Fairchild in 1965, when Moore was director of research and development. Electronics magazine asked him for a prediction covering the next ten years of semiconductor components. He responded with a piece titled "Cramming more components onto integrated circuits." At that point, the number of components per integrated circuit had been doubling annually. Moore projected that the rate would continue for at least another decade, anticipating as many as 65000 components on a single quarter-square-inch semiconductor by 1975. His focus joined greater complexity to minimum component costs, rather than simply measuring how quickly a computer could perform a task.
At the 1975 IEEE International Electron Devices Meeting, Moore revised the pace he expected. Complexity would continue doubling annually until about 1980, then double approximately every two years. He identified several contributors: metal-oxide-semiconductor technology, increasing die sizes alongside decreasing defect densities, finer minimum dimensions, and improvements in circuit and device design. Caltech professor Carver Mead popularized the term Moore's law shortly afterward. Manufacturers adopted it as a goal, using the forecast for long-term planning and research targets. An observation of past production thus became something companies actively worked toward, giving it a role beyond predicting the future from earlier measurements.
The eighteen-month interval came from a separate calculation by Moore's colleague David House. In 1975, the Intel executive linked the revised transistor forecast to chip performance, predicting that performance would roughly double every eighteen months without increased power consumption. His reasoning combined shrinking transistor dimensions with Dennard scaling. Robert Dennard had formulated that scaling relationship at IBM in 1974: as MOS transistors became smaller, power density stayed constant, keeping power use proportional to area. More transistors and the effects of shrinking dimensions together supported House's performance prediction. It concerned a different result from the component-count relationship, even though the two became closely associated.
Building those denser circuits depended on successive technical advances. Jack Kilby's germanium hybrid integrated circuit at Texas Instruments in 1958 was followed by Robert Noyce's silicon monolithic chip at Fairchild in 1959. Chih-Tang Sah and Frank Wanlass developed the complementary metal-oxide-semiconductor process at Fairchild in 1963. Dennard developed dynamic random-access memory at IBM in 1967. Later, chemically amplified photoresist increased sensitivity to ultraviolet light, and deep ultraviolet excimer laser photolithography advanced fabrication. Interconnect improvements in the late 1990s helped wafer yield, added layers of metal wiring, allowed closer device spacing, and reduced electrical resistance. Progress involved the connections between devices as well as the devices themselves.
Moore's law also has an expensive manufacturing counterpart. As computer power became cheaper for consumers, research, manufacturing, and testing costs rose with successive chip generations. The cost of fabrication tools, principally extreme ultraviolet lithography, doubles every 4 years. Rising expenses helped motivate Moore's second law, also called Rock's law after Arthur Rock: the capital cost of a semiconductor fabrication plant increases exponentially over time. This creates a separate economic pressure on continued scaling. A falling price for computing power can coexist with increasingly costly production facilities, so the consumer's price and the manufacturer's investment move along different paths.
Technical limits changed the industry as well. Dennard scaling ended in the mid-2000s, and microprocessor architects reported industry-wide advancement slowing below the predicted pace from around 2010. Smaller devices make controlling current in a thin channel more difficult. Modern nanoscale transistors commonly use multiple gates; the FinFET places gate dielectric on three sides of its channel, while a gate-all-around structure provides better gate control. A Toshiba team led by Fujio Masuoka demonstrated a vertical nanowire gate-all-around transistor in 1988. These designs address the behavior of extremely small devices, adding engineering demands to the challenge of fitting more components into integrated circuits.
Another route adds height. Three-dimensional NAND stacks flash memory cells vertically, increasing the transistor population on a flash chip. Toshiba announced this approach in 2007, and Samsung commercially manufactured V-NAND in 2013. Samsung later combined vertical memory with stacked integrated circuits, producing a 512 GB flash chip in 2017 and a 1 TB chip in 2019. Meanwhile, assessments of Moore's law continued to differ: in September 2022, Nvidia's Jensen Huang considered it dead, while Intel's then-chief executive Pat Gelsinger held the opposite view.